The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the electronic design methodologies. In modern electronic circuits, the total number of transistors has increased; geometries have become smaller; and clock frequencies have increased over time. Errors on silicon have become prohibitively expensive. To address the ever increasing total number of transistors and clock frequencies, three-dimensional (3D) integrated circuits (3D-ICs), die-stacking, and non-planar transistors such as Fin Field Effect Transistor (FinFET) have been developed.
Nonetheless, such 3D-ICs, die-stacking, and non-planar transistors intrinsically cause thermal issues and electromagnetic issues due to, for example, the lack of readily accessible thermal dissipation channel, when compared with a single chip in a package on a printed circuit board (PCB). Through costly experiments and mistakes, thermal vias and perhaps through silicon vias (TSVs) are developed to counter the thermal issues. As a result, there has been a long-felt need for pre-silicon analysis capabilities using the data in the layout artwork.
Some conventional approaches attempt to tackle such needs by modeling electronic circuits with layout artwork. Such conventional approaches are nevertheless limited by the size of layout artwork for modern electronic designs. For example, a GDSII file for a modern semiconductor chip may easily occupy hundreds of gigabytes, terabytes, or even larger space on disk. To further exacerbate these challenges and problems, such humongous sizes of modern layout artwork are merely the sizes of the corresponding layout artwork, and an actual model representing an entire semiconductor chip may be even larger to fit into the memory of even the most powerful computing systems, not to mention performing any analyses with such a model.
As a result, conventional approaches try to avoid such insurmountable obstacles by simply modeling a circuit component, such as a FinFET or a small cell or block. During analyses with a model for such a small, discrete component that is not tied to any other circuit components as in real world applications, the analysis results would be educated guess at best yet provide limited information or insight, if any, to help designers understand how the modeled circuit component would behave in real world applications.
Similarly, modern electronic designs are more sensitive to electromagnetic interferences. Even for planar circuit features, modern electronic designs often have a large number of layers stacking on top of each other. On the other hand, conventional electromagnetic analyses adopt pseudo-3D (also known as 2.5D, or three-quarter perspective) methodologies. The analysis results thus require certain empirical or a posteriori corrections or modifications to approximate what actually occurs in a real, multi-layer electronic circuit. These conventional electromagnetic analyses have encountered greater difficulties in determining the behaviors of 3D-ICs or electronic designs having non-planar transistors or may simply reduce such 3D-ICs or non-planar circuit components to a simplified form to fit their analysis capabilities and thus lose resolution and details of the behaviors of such non-planar circuit features.
Therefore, it is important for an EDA tool to efficiently, effectively, and accurately implement electronic designs with physical simulations using layout artwork to address at least the aforementioned shortcomings of conventional approaches.